-- Copyright James McGill, 2010
-- Author: James McGill (jmcgill@plexer.net)

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity clock_generator_test is
end clock_generator_test;
 
architecture behavior OF clock_generator_test IS 
    -- UUT
    COMPONENT clock_generator
    PORT(
         reset : IN  std_logic;
         clock_50mhz : IN  std_logic;
			clock_48mhz : INOUT std_logic;
			clock_24mhz : INOUT std_logic;
         clock_8mhz : INOUT  std_logic;
			clock_4mhz : INOUT  std_logic;
			clock_2mhz : INOUT  std_logic;
         clock_1mhz : INOUT  std_logic;
         locked : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal reset : std_logic := '0';
   signal clock_50mhz : std_logic := '0';

 	--Outputs
   signal clock_24mhz : std_logic;
	signal clock_48mhz : std_logic;
	signal clock_8mhz : std_logic;
	signal clock_4mhz : std_logic;
	signal clock_2mhz : std_logic;
   signal clock_1mhz : std_logic;
   signal locked : std_logic;

   -- Clock period definitions
   constant clock_50mhz_period : time := 20 ns;
 
begin
 
	-- Instantiate the Unit Under Test (UUT)
   uut: clock_generator PORT MAP (
          reset => reset,
          clock_50mhz => clock_50mhz,
			 clock_24mhz => clock_24mhz,
			 clock_48mhz => clock_48mhz,
          clock_8mhz => clock_8mhz,
			 clock_4mhz => clock_4mhz,
			 clock_2mhz => clock_2mhz,
          clock_1mhz => clock_1mhz,
          locked => locked
        );

   -- Clock process definitions
   clock_50mhz_process :process
   begin
		clock_50mhz <= '0';
		wait for clock_50mhz_period / 2;
		clock_50mhz <= '1';
		wait for clock_50mhz_period / 2;
   end process;
 
   -- Stimulus process
	-- NOTE(jmcgill): This runs in parallel with the above.
   stim_proc: process
   begin		
	   reset <= '1';
      wait for clock_50mhz_period * 10;
      reset <= '0';
      wait;
   end process;

end;
